Built-in self-test (BIST) is a design-for-test methodology that permits a circuit to test itself using embedded test logic. When the circuit-under-test is a logic circuit, the BIST is referred to as logic built-in self-test (LBIST). Comparing with traditional automatic test pattern generation (ATPG), LBIST does not rely on pre-computed test patterns to achieve high test coverage. Test stimuli in LBIST are instead generated by a pseudo-random pattern generator. Examples of pseudo-random pattern generators include linear feedback shift register (LFSR) and cellular automata (CA).
LBIST is a scan-based test. Like other scan-based test technique, circuit testing may cause excessive circuit switching activity compared to normal operation of the circuit. Such excessive switching activity can occur during scan chain shift cycles, capture cycles or both. Higher switching activity leads to higher power dissipation and higher peak supply currents. High power dissipation may in turn lead to hot spots that could damage the circuit. Excessive peak supply currents may cause IR-drop and di/dt problem, which, in turn, causes circuit-under-test to fail during testing due to additional gate delay.
Several techniques have been proposed in the past to reduce switching activity caused by scan shift. For example, logic gates may be inserted to hold scan cell outputs at constant values during scan shift cycles. These extra logic gates may, however, degrade circuit performance. Some other techniques are based on low toggling pseudo-random test patterns. The probability of any bit in conventional pseudo-random test patterns being “0” (or “1”) is 50%. By contrast, some adjacent bits in low toggling pseudo-random test patterns are highly correlated, resulting in low switching activity during scan shift cycles. The following papers, which are incorporated herein by reference, include examples of generating low toggling pseudo-random test patterns: S. Wang and S. K. Gupta, “LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation,” in Int. Test Conf., 1999, pp. 85-94; M. Nourani, M. Tehranipoor, and N. Ahmed, “Low-Transition Test Pattern Generation for BIST-Based Application,” in IEEE Tran. on Comp., Vol. 57, No. 3, March 2008, pp. 303-315; X. Lin, and J. Rajski, “Adaptive Low Shift Power Test Pattern Generator,” in Asian Test Symp., 2010, pp. 355-360; and J. Rajski, J. Tyszer, G. Mrugalski, and B. Nadeau-Dostie, “Test Generator with Preselected Toggling for Low Power Build-In Self-Test,” in VLSI Test Symp., 2012, pp. 1-6. While reducing power consumption during scan shift cycles, the use of low toggling pseudo-random test patterns tends to affect test coverage because the randomness of bit values in low toggling pseudo-random test patterns are decreased.
Weighted random pattern generation techniques have been employed to improve detection probability of conventional pseudo-random test patterns. In this approach, outputs of a conventional pseudo-random pattern generator are intentionally biased to create test sequence with non-uniform distributed ones and zeros for some selected bits. As noted above, bits in conventional pseudo-random test patterns have equal probability values of being “0” and “1”. Bits in weighted random test patterns, by contrast, are selected to be assigned different probability values of being “1” and “0” based on faults to be detected. The probability value of being “0” (or “1”) for a bit is referred to as the weight value of the bit. Different faults may require different biases of the test stimulus combination. Thus, multiple weight assignments are often required to detect majority of faults by a small number of random test patterns.
Various techniques may be used to select bits and their weight values to achieve high test coverage. One technique based on analysis of fault detection probabilities is disclosed by H.-J. Wunderlich, “Multiple Distributions for Biased Random Test Patterns,” in Int. Test. Conf., 1988, pp. 236-244, which is incorporated herein by reference. Another technique is based on analysis of deterministic test patterns generated for the same circuit. In this technique, ones and zeros of a bit in a set of deterministic test patterns may be counted to derive the weight value for the bit. Three published papers, I. Pomeranz, and S. M. Reddy, “3-Weighted Pseudo-Random Test Generation Based on a Deterministic Test Set,” in IEEE Trans. on CAD, July 1993, pp. 1050-1058, S. Wang, “Low Hardware Overhead Scan Based 3-Weight Weighted Random BIST,” in Int. Test Conf., 2001, pp. 868-877, and S. Ghosh, E. Macdonald, S. Basu, and N. A. Touba, “Low-Power Weighted Pseudo-Random BIST Using Special Scan Cells,” in GLSVLSI, April 2004, are examples of using this technique, which are incorporated herein by reference. In these examples, a NOT, AND and OR network is inserted between outputs of a conventional pseudo-random pattern generator and serial inputs of scan chains to produce bit values with weight values different from 50%. To load these bit values to corresponding scan cells, control logic based on an on-chip ROM storing weight value and assignment information is employed.
Two of the above-mentioned articles (S. Wang, et al. and S. Ghosh, et al.) describe how both high test coverage and low switching activity can be achieved for a LBIST-based application by coupling a weighted random pattern generation technique with a low toggling pseudo-random test pattern technique. It is desirable, however, to develop techniques that can obtain similar or better results without using an on-chip ROM.